Method of manufacturing a semiconductor device having a trench isolation structure

ABSTRACT

In a method of manufacturing a semiconductor device, a silicon oxide film is embedded in a trench portion for isolating the device forming regions on a silicon substrate, and a silicon nitride film, a polysilicon film, and a pad insulating film left on the device forming regions on a silicon substrate are removed to expose a surface of the semiconductor substrate, wherein the polysilicon film is removed by isotropic wet etching.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to improvement of a manufacturingmethod of a semiconductor device having a miniature structure withtrench isolation.

[0003] 2. Background Art

[0004] In recent years, the demand for semiconductor devices hasincreased rapidly with marked spread of information equipment such ascomputers or the like. In terms of functionality, semiconductor deviceshaving large memory capacity and capable of high-speed operation arerequired. To satisfy those demand and requirements, technicaldevelopments for increasing the integration density, the response speed,and the reliability of semiconductor devices are now being made.

[0005] The trench isolation as a device isolation method insemiconductor devices is effective for the device miniaturizationbecause what is called bird's beak is less prone to be formed in thetrench isolation than in the LOCOS isolation. A manufacturing methodincluding trench isolation will be described below.

[0006] As shown in FIG. 17, patterns of a pad insulating film 2 (siliconoxide film), a polysilicon film 3, and a silicon nitride film 4 areformed on a p-type silicon substrate 1.

[0007] Then, as shown in FIG. 18, a trench 5 is formed by etching thesilicon substrate 1 by using the silicon nitride film 4 as a mask.Alternatively, the silicon nitride film 4, the polysilicon film 3, thepad insulating film 2, and the silicon substrate 1 may be etched at onetime by using a resist mask.

[0008] Then, as shown in FIG. 19, after the trench 5 is filled in bydepositing a silicon oxide film 6 by CVD, for example, the part of thesilicon oxide film 6 above the silicon nitride film 4 is removed by CMP,for example. Part of the remaining silicon oxide film 6 is thereafterremoved by using hydrofluoric acid, whereby the level difference isreduced.

[0009] Then, as shown in FIG. 20, the silicon nitride film 4 is removedby using phosphoric acid, for example.

[0010] Then, the polysilicon film 3 shown in FIG. 20 is removed by usinga plasma etching apparatus, whereby the pad insulating film 2 is exposedas shown in FIG. 21.

[0011] Then, the pad insulating film 2 shown in FIG. 21 is removed byusing hydrofluoric acid, whereby the surface of the silicon substrate 1is exposed as shown in FIG. 22.

[0012] Then, as shown in FIG. 23, a gate insulating film 7 is formed,and a doped polysilicon film 8, a metal silicide film 9, and aninsulating film 10 are formed thereon. Thereafter, a gate electrode isformed by patterning and etching the lamination films. A MOS transistoris thereafter formed by forming a pair of n-type source and drainregions 11 by ion implantation.

[0013] In the above manufacturing process, the thickness of the padinsulating film 2 has been reduced with the recent miniaturization ofdevices. As a result, the etching damage that occurs in removing thepolysilicon film 3 on the pad insulating film 2 tends to encompass thesilicon substrate 1.

[0014] Where the trench-filling silicon oxide film 6 is formed byHDP-CVD, it has an overhang as shown in part A in FIG. 24. This causesanother problem that polysilicon etching residues 12 tend to occur asshown in FIG. 25 when the polysilicon film 3 is etched.

[0015] Because of a small selective etching ratio of the polysiliconfilm 3 to the pad insulating film 2, the thickness of the remaining padinsulating film 2 varies in its plane. Therefore, where an impurity forcontrolling the threshold voltage of the transistor is implanted in thestate of FIG. 21, a problem occurs that the uniformity of the thresholdvoltage is low. This phenomenon is remarkable when the implantationenergy is low.

[0016] Where the trench-filling silicon oxide film 6is formed byHDP-CVD, for example, there is a problem that at the time of a heattreatment the thickness of the pad insulating film 2 is increased asdenoted by reference numeral 19 in FIG. 26 because of degassing from thesilicon oxide film 6 (HDP-CVD film). This phenomenon is particularlyremarkable in a wafer peripheral portion, and causes a problem that theuniformity of the threshold voltage is low in a case where an impurityfor threshold voltage control is implanted.

[0017] There is another problem that if the above-mentioned heattreatment is performed in a nitriding atmosphere, the silicon substrate1 is nitrided through the pad insulating film 2. In particular, thisphenomenon occurs in a case where the pad insulating film 2 has thinportions in the vicinity of the isolation oxide film 6 as shown in partB in FIG. 27. And this phenomenon is particularly remarkable in a casewhere the pad insulating film 6 is formed again (a process of FIGS.21→FIGS. 22→FIG. 21). In nitrided regions, the thickness of the gateoxide film 7 is small and hence the gate breakdown voltage is low; thatis, the reliability of the gate insulating film 7 is lowered.

[0018] FIGS. 28-31 show another problem of roughening of the trenchportion. In each of FIGS. 28-31, the left-hand part shows a deviceportion (or a device forming portion) and the right-hand part shows amark portion.

[0019] The conventional trench isolation has a problem that, because ofa small level difference, alignment marks cannot be detected at ensuingsteps. To solve this problem, after formation of the trench isolationstructure, the portions other than mark portions are covered with aresist 21 (see FIG. 28) and then the silicon oxide film 6 that is buriedin the trench portion 22 is removed only in the mark portions to formsteps (see FIG. 29). Then, an impurity for well formation or control ofthe threshold voltage of the transistor is implanted (see FIG. 30).However, there is a problem that the portions where the siliconsubstrate 1 is exposed, in particular, the trench portions, areroughened in a heat treatment for activating the impurity (see FIG. 31).The roughening may lower the alignment accuracy. It is considered thatthis phenomenon relates to the etching damage or stress that occurs atthe time of the formation of the trench isolation structure. Thisphenomenon is particularly remarkable in a case where the trenchisolation structure is formed in a high-temperature, non-oxidizingatmosphere.

SUMMARY OF THE INVENTION

[0020] The present invention has been made to solve the above problemsin the art, and an object of the invention is therefore to increase thereliability of a gate oxide film and improve the junction leakcharacteristic by wet-removing a silicon film on an insulating film oroptimizing treatment/film-forming steps in a trench isolation process.

[0021] According to one aspect of the present invention, in a method ofmanufacturing a semiconductor device,

[0022] a pad insulating film, a polysilicon film, and a silicon nitridefilm are formed sequentially on a semiconductor substrate. A trenchportion for isolating device forming regions on the semiconductorsubstrate is formed by selectively etching the silicon nitride film, thepolysilicon film, the pad insulating film, and the semiconductorsubstrate. A silicon oxide film is embedded in the trench portion forisolating the device forming regions. The silicon nitride film, thepolysilicon film, and the pad insulating film are removed to expose asurface of the semiconductor substrate. Then, a circuit element isformed on the exposed surface of the semiconductor substrate.Particularly in the above method, the polysilicon film is removed byisotropic wet etching.

[0023] According to another aspect of the present invention, in a methodof manufacturing a semiconductor device, at least a gate insulatingfilm, a polysilicon film, and an upper insulating film are sequentiallyformed on the exposed surface of the semiconductor substrate asdescribed above, and a gate electrode is formed by patterning the upperinsulating film, the polysilicon film, and the gate insulating film byanisotropic etching. Then, isotropic wet etching is performed to removepolysilicon on the surface of the semiconductor substrate.

[0024] According to still another aspect of the present invention, in amethod of manufacturing a semiconductor device, a storage node is formedon an interlayer insulating film that is formed on a semiconductorsubstrate. The surface of the storage node is roughened. Then,wet-etching is performed on the surface of the interlayer insulatingfilm.

[0025] Other and further objects, features and advantages of theinvention will appear more fully from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

[0026]FIG. 1 is a cross sectional view of a semiconductor device toexplain a first embodiment of the present invention.

[0027]FIGS. 2 and 3 are cross sectional views of a semiconductor deviceto explain a second embodiment of the present invention.

[0028]FIG. 3 is a cross sectional view of a semiconductor device toexplain a first embodiment of the present invention.

[0029]FIG. 4 is a cross sectional view of a semiconductor device toexplain a third embodiment of the present invention.

[0030]FIG. 5 is a cross sectional view of a semiconductor device toexplain a fifth embodiment of the present invention.

[0031] FIGS. 6 to 9 are cross sectional views of a semiconductor deviceto explain a sixth embodiment of the present invention.

[0032] FIGS. 10 to 13 are cross sectional views of a semiconductordevice to explain a seventh embodiment of the present invention.

[0033] FIGS. 14 to 16 are cross sectional views of a semiconductordevice to explain a eighth embodiment of the present invention.

[0034]FIGS. 17 through 23 are cross sectional views for explaining aprocess of a manufacturing method of a semiconductor device in aconventional art.

[0035]FIGS. 24 through 27 are cross sectional views respectively forexplaining a manufacturing method of a semiconductor device in aconventional art.

[0036]FIGS. 28 through 31 are cross sectional views for explaininganother process of a manufacturing method of a semiconductor device in aconventional art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] Some preferred embodiments of the present invention will behereinafter described with reference to the accompanying drawings. Theparts in the drawings that are the same as or corresponding to eachother are given the same reference numerals and their descriptions willbe simplified or omitted.

Embodiment 1

[0038] A first embodiment of the invention will be described by usingFIGS. 17-23 in a diverted manner. This embodiment relates to improvementof the conventional trench isolation process.

[0039] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-20are executed.

[0040] In the conventional step that causes the transition from FIG. 20to FIG. 21, the polysilicon film 3 is subjected to plasma etching. Incontrast, in this embodiment, the polysilicon film 3 is removed by wetetching.

[0041] Where the polysilicon film 3 is removed by wet etching, thesilicon substrate 1 is not damaged. Therefore, this measure provides anadvantage that the reliability of the gate insulating film 7 to beformed on this surface is increased and the junction leak current in thesource and drain regions is decreased.

[0042] At the stage of FIG. 20, the trench isolation structure may besuch that the trench oxide film 6 is buried so as to form an overhang asshown in part A in FIG. 24. Even where the trench isolation structurehas such a shape, if the polysilicon film 3 is removed by wet etchingwhich is isotropic, no etching residue of the polysilicon film 3 remainsas shown in FIG. 1, to provide advantages that, for example, the rate ofoccurrence of short-circuiting between gate lines is reduced and therate occurrence of defects due to peeling-off of polysilicon residues.

[0043] The steps of FIG. 22 and the following figures may be the same asin the conventional process and hence the explanation will not berepeated here.

[0044] By using, as a wet etching liquid, aqueous ammonia or a mixedliquid of aqueous ammonia and a hydrogen peroxide solution, a largeselective etching ratio to the pad insulating film 2 can be obtained andhence the uniformity of the thickness of the remaining pad insulatingfilm 2 is improved. Therefore, for example, when an impurity forthreshold voltage control is implanted through the pad insulating film 2(see FIG. 30), the uniformity of the threshold voltage in the wafersurface can be improved. Although the above description is directed tothe trench isolation, equivalent advantages can be obtained also for thepolysilicon buffer LOCOS isolation.

[0045] As described above, according to this embodiment, the polysiliconfilm on the pad insulating film that is formed on the substrate iswet-removed after formation of the trench isolation structure. Thismakes it possible to, for example, increase the reliability of the gateoxide film, reduce the junction leak current, decrease polysiliconetching residues, and increase the uniformity of the threshold voltage.

[0046] In the above embodiments, in FIG. 17, a polysilicon film 3 isformed on a pad insulating film 2. However, in other modification orvariation, the polysilicon film 3 may not be included. This applies alsoto the other embodiments to be described hereinbelow.

Embodiment 2

[0047] A second embodiment of the invention will be described by usingFIGS. 17-23 again. This embodiment relates to improvement of theconventional trench isolation process.

[0048] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-20are executed.

[0049] Among those steps, at the stage of FIG. 18, oxidation may beperformed after the trench etching to eliminate etching damage of thesilicon substrate 1. At the stage of FIG. 19 or ensuing stages, a heattreatment may be performed after burying the trench-filling CVD oxidefilm 6 to stabilize the wet etching rate etc. of the CVD oxide film 6.

[0050] Depending on the heat treatment conditions (e.g., the heattreatment may be performed at a low-temperature of 1,000° C. or less),there may occur a case that stress occurring in the polysilicon film 3causes a damage or split 13 in the polysilicon film 3 as shown in FIG.2. In this case, if the polysilicon film 3 were removed by dry etchingas in the conventional process in which the selective etching ratio ofthe polysilicon film 2 to the pad insulating film 2 is small, there isfear that as shown in FIG. 3 the silicon substrate 1 would be etched asindicated by reference numeral 14 in FIG. 3 at the portion where thepolysilicon film 3 has the damage 13.

[0051] This phenomenon can be avoided in the process of the firstembodiment in which the polysilicon film 3 is removed by wet etching.That is, by virtue of a large selective etching ratio of the polysiliconfilm 3 to the pad insulating film 2, the silicon substrate 1 is notetched even if the polysilicon film 3 has the damage or lost portion 13.However, if a hydrofluoric acid solution treatment is performed beforethe polysilicon etching to remove a native oxide film on the polysiliconfilm, there is fear that the pad insulating film 3 and hence the siliconsubstrate 1 may be etched irrespective of whether dry etching or wetetching is employed. This event should be avoided.

[0052] As described above, conventionally, the heat treatment of thetrench oxide film 6 is performed at 1,000° C. or less. In contrast, inthis embodiment, the heat treatment of the trench oxide film 6 isperformed at 1,050° C. or more.

[0053] The heat treatment at 1,050° C. or more provides an advantagethat stress-induced damages are less prone to occur in the polysiliconfilm 3, thereby the stress is hard to be entered into the polysiliconfilm 3.

[0054] Then, in the step of FIG. 20, the polysilicon film 3 is removedby wet etching as described in the first embodiment. The combination ofthe steps of performing the heat treatment of the trench oxide film 6 at1,050° C. or more and then removing the polysilicon film 3 by wetetching further increases the margin.

[0055] The steps of FIG. 21 and the following steps may be the same asin the conventional process and hence the duplicated explanations arenot described here.

[0056] As described above, according to this embodiment, the polysiliconfilm on the pad insulating film that is formed on the silicon substrateis wet-removed after the heat treatment at 1,050° C. or more. This makesit possible, for example, to increase the reliability of the gate oxidefilm.

Embodiment 3

[0057] A third embodiment of the present invention will be described byusing FIGS. 17-23 again. This embodiment relates to improvement of theconventional trench isolation process.

[0058] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-20are executed.

[0059] Where the trench-filling silicon oxide film 6 is formed byHDP-CVD, for example, in the step of FIG. 19 among the above steps,there is a problem that at the time of a heat treatment the thickness ofthe pad insulating film 2 is increased as denoted by reference numeral19 in FIG. 26 because of degassing from the trench oxide film 6 (HDPCVDfilm).

[0060] In this embodiment, as a countermeasure against the degassingthat occurs when the trench oxide film 6 (TEOS oxide film or HDP-CVDfilm) is annealed, a CVD oxide film 20 is deposited by using asilane-type or dichlorosilane-type gas as shown in FIG. 4. The oxidefilm 20 thus formed is different from the TEOS oxide film in thedensity, hygroscopicity, etc., degassing from the trench oxide film 6can be suppressed. Therefore, there does not occur the event that thepad oxide film 2 is made thicker when the trench oxide film 6 isannealed.

[0061] Another effective countermeasure against the degassing at thetime of the annealing of the trench oxide film 6 is to modify thesurface layer of the trench oxide film 6 (TEOS oxide film) by a heattreatment in an oxidizing atmosphere and then anneal the trench oxidefilm 6.

[0062] A still another effective countermeasure against the degassing isto perform a short-time, rapid heat treatment, for example, RTA (rapidthermal annealing) as performed in a single-wafer heat treatmentapparatus, on the trench oxide film 6 and then anneal the trench oxidefilm 6 by using a tube-type heat treatment apparatus, for example.

[0063] As described above, according to this embodiment, the cover filmis deposited before the annealing of the trench oxide film (TEOS oxidefilm), the heat treatment is performed after the trench oxide film issubjected to oxidation, or the trench oxide film is processed by atube-type heat treatment apparatus after being subjected to RTA with asingle-wafer heat treatment apparatus. This makes it possible tosuppress the degassing from the TEOS film.

Embodiment 4

[0064] A fourth embodiment of the present invention will be described byusing FIGS. 17-23 again. This embodiment relates to improvement of theconventional trench isolation process.

[0065] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-21are executed.

[0066] Where the heat treatment of the trench oxide film 6, for example,is performed in a nitriding atmosphere in the steps up to the state ofFIG. 21, there may occur an event that the silicon substrate 1 isnitrided through the pad insulating film 2. This phenomenon is moreprone to occur in a state that the pad insulating film 2 has thinportions in the vicinity of the isolation oxide film 6 as shown in partB in FIG. 27. The later-formed gate oxide film 7 has a small thicknessabove nirided portions of the silicon substrate 1. Therefore, the gatebreakdown voltage may be reduced, possibly lowering the reliability ofthe gate insulating film 7.

[0067] When the surface of the silicon substrate 1 has been nitrided inregions in the vicinity of the isolation oxide film 6 where thethickness of the pad insulating film 2 is decreased as shown in FIG. 27,in this embodiment the pad insulating film 2 is removed by using ahydrofluoric acid solution in the step of FIG. 21 and then the nitridelayers are removed by processing the surface with a phosphoric acid typesolution to expose the surface of the silicon substrate 1 as shown inFIG. 22.

[0068] Then, the MOS transistor is formed as shown in FIG. 23. Theremoval of nitride layers increases the reliability of the gateinsulating film 7.

[0069] As described above, according to this embodiment, beforeformation of the gate insulating film, the silicon substrate iswet-etched with a phosphoric acid type solution to remove nitridedlayers. This makes it possible to increase the reliability of the gateoxide film.

Embodiment 5

[0070] A fifth embodiment of the present invention will be described byusing FIGS. 17-23 again. This embodiment relates to improvement of theconventional trench isolation process.

[0071] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-21are executed.

[0072] In the fourth embodiment described above, the silicon substrate 1is processed with a phosphoric acid type solution upon its exposure.However, there is fear that the silicon substrate 1 may be roughened bythe phosphoric acid treatment in non-nitrided regions (i.e., the marginfor the roughening is small). The roughening of the silicon substrate 1may lower the reliability of the gate oxide film 7.

[0073] In view of the above, in this embodiment, after only the thinnedportions (see FIG. 27) of the pad insulating film 2 are removed as shownin FIG. 5 in the step of FIG. 21, nitride layers are removed by aphosphoric acid treatment and then the remaining portion of the padinsulating film 2 is removed to expose the surface of the siliconsubstrate 1 as shown in FIG. 22. According to this method, sincenon-nitrided portions of the silicon substrate 1 are not exposed tophosphoric acid, the margin for the roughening is increased and hencethe reliability of the gate insulating film 7 is increased.

[0074] As described above, according to this embodiment, beforeformation of the gate insulating film, only the portions of the siliconsubstrate under thinned portions of the pad oxide film are exposed,nitride layers are removed by wet processing, and then the remainingportion of the pad oxide film is etched. This makes it possible toincrease the reliability of the gate oxide film.

Embodiment 6

[0075] A sixth embodiment of the present invention will be described byusing FIGS. 17-23 again. This embodiment relates to improvement of theconventional trench isolation process.

[0076] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-21are executed.

[0077] In the step of FIG. 21, a level difference may occur between thesurfaces of the trench isolation film 6 and the silicon substrate 1 asshown in FIG. 6. In this case, there may occur a problem that residues15 of the doped polysilicon film 8 remain at the edge of the trenchisolation film 6 as shown in FIG. 7 when the gate electrode pattern isformed.

[0078] In view of the above, in this embodiment, polysilicon isotropicwet etching is performed after the gate electrode is formed byanisotropic etching, whereby the polysilicon residues 15 at the edge ofthe trench isolation film 6 are removed as shown in FIG. 8. At thistime, it is necessary to prevent the underlying silicon substrate 1 frombeing exposed as a result of etching of the gate insulating film 7during the etching of the gate electrode.

[0079] Alternatively, etching residues at the edge (i.e., the step) ofthe trench isolation film 6 can be prevented by performing polysiliconwet etching after performing anisotropic etching halfway on the dopedpolysilicon film 8 of the gate electrode as shown in FIG. 9. That is,the isotropic wet etching on the remaining gate electrode is performedafter the anisotropic etching on the gate electrode is stopped halfway.

[0080] Since the subsequent steps may be the same as in the conventionalprocess, they are not described in detail here.

[0081] As described above, according to this embodiment, isotropic wetetching is performed after anisotropic etching is performed on the gateelectrode. Alternatively, isotropic wet etching is performed on theremaining gate electrode after anisotropic etching on the gate electrodeis stopped halfway. This makes it possible to decrease polysiliconetching residue.

Embodiment 7

[0082] A seventh embodiment of the present invention will be describedby using FIGS. 17-23 again. This embodiment relates to improvement ofthe conventional trench isolation process.

[0083] In the manufacturing method according to this embodimentincluding trench isolation, first, the conventional steps of FIGS. 17-21are executed.

[0084] If the level difference of the trench isolation structure issmall in the step of FIG. 21, there may occur a problem that alignmentmarks cannot be detected in ensuing steps. To solve this problem,conventionally, after formation of the trench isolation structure, theportions other than mark portions are covered with a resist 21 (see FIG.28) and then the silicon oxide film 6 that is buried in the trenchportion 22 is removed only in the mark portions to form steps (see FIG.29). Then, an impurity for well formation or control of the thresholdvoltage of the transistor is implanted (see FIG. 30). However, there isa problem that the portions where the silicon substrate 1 is exposed, inparticular, the trench portions, are roughened in a heat treatment foractivating the impurity (see FIG. 31). The roughening may lower thealignment accuracy.

[0085] In contrast, in this embodiment, as a countermeasure against theroughening of the substrate 1 in the trench isolation mark portions,steps shown in FIGS. 10-13 are performed. In each of FIGS. 10-13, theleft-hand part shows a device portion (or a device forming portion) andthe right-hand part shows a mark portion.

[0086] First, as shown in FIG. 10, ion implantation for thresholdvoltage control or well formation is performed on the area including themark portions. Since the surface of the silicon substrate 1 is coveredwith the insulating film 2, the silicon substrate 1 is not roughenedeven when a heat treatment for activation is performed. Therefore, thealignment accuracy is improved.

[0087] Then, the device portion is covered with a resist 21 as shown inFIG. 11.

[0088] Then, as shown in FIG. 12, the trench insulating film 6 isremoved in the mark portions to form steps.

[0089] Then, as shown in FIG. 13, a gate insulating film 7, a dopedpolysilicon film 8, a metal silicide film 9, and an insulating film 10,and source and drain regions are formed as a transistor.

[0090] Although the above process is directed to the case of using thetrench isolation, the method of this embodiment is also effective forthe LOCOS isolation method in a case where an isolation oxide film isremoved in mark portions.

[0091] As described above, according to this embodiment, in both of thedevice portion and the mark portions, an impurity is implanted throughthe pad insulating film and then annealing is performed. This makes itpossible to improve the alignment accuracy.

Embodiment 8

[0092] An eighth embodiment of the present invention will be describedwith reference to FIGS. 14-16. In this embodiment, wet etching of asilicon insulating film is applied to formation of a roughened-surfacecapacitor of a storage node.

[0093]FIG. 14 is a sectional view showing the structure of a DRAM formedby applying a surface-roughening process to a capacitor. A descriptionwill be made of a case where polysilicon wet etching is applied to thisstructure.

[0094] A roughened-surface capacitor is formed in the following manner.After a storage node 16 is formed as shown in FIG. 15, silicon particles17 are formed on the entire wafer surface. Then, as shown in FIG. 16,the silicon particles 17 on an interlayer insulating film 18 areremoved.

[0095] If the silicon particles 17 are removed by using a wet etchingliquid, particularly aqueous ammonia, the graininess of the roughenedsurface becomes high because the etching rate is such directivity as tobe high in the direction perpendicular to the surface. This provides anadvantage that the capacitance is increased.

[0096] Even where the silicon particles 17 on the interlayer insulatingfilm 18 are removed by dry etching, it is effective to also perform wetetching to remove silicon particle residues on the interlayer insulatingfilm 18.

[0097] Further, there may occur a case that silicon particles areslightly formed on an interlayer insulating film 18 also when astructure shown in FIG. 16 is formed by selectively roughening thesurface of a storage node 16. In this case, silicon wet etching may beperformed to remove those silicon particles and increase the graininessof the roughened surface.

[0098] As described above, according to this embodiment, the siliconinterlayer insulating film is wet-etched after roughening of the storagenode. This makes it possible to increase the capacitance and removepolysilicon residues from the roughened surface more reliably.

[0099] The embodiments of the invention have been described above. It isnoted that these embodiments can be practiced in combination whennecessary or with proper selection from among them.

[0100] Having the above features, the manufacturing methods of asemiconductor device according to the present invention provides thefollowing advantages.

[0101] A polysilicon film on a pad insulating film that is formed on asubstrate is wet-removed after formation of a trench isolationstructure. This makes it possible to, for example, increase thereliability of a gate oxide film and reduce the junction leak current.

[0102] A cover film is deposited before annealing of a trench oxide film(TEOS oxide film), a heat treatment is performed after a trench oxidefilm is subjected to oxidation, or a trench oxide film is processed by atube-type heat treatment apparatus after being subjected to RTA with asingle-wafer heat treatment apparatus. This makes it possible tosuppress degassing from the TEOS film, thereby, for example, increasingthe reliability of a gate oxide film.

[0103] Before formation of a gate insulating film, nitride layers areremoved by wet processing, that is, by wet-etching a silicon substratewith a phosphoric acid solution. This makes it possible to increase thereliability of the gate oxide film.

[0104] Before formation of a gate insulating film, only the portions ofa silicon substrate under thinned portions of a pad oxide film areexposed, nitride layers are removed by wet processing, and then theremaining pad oxide film is etched. This makes it possible to increasethe reliability of the gate oxide film.

[0105] Isotropic wet etching is performed after anisotropic etching isperformed on the gate electrode. Alternatively, isotropic wet etching isperformed on the remaining gate electrode after anisotropic etching on agate electrode is stopped halfway. This makes it possible to decreasepolysilicon etching residue.

[0106] In both of a device portion and mark portions in a chip or wafer,an impurity is implanted through a pad insulating film and thenannealing is performed. This makes it possible to improve the alignmentaccuracy.

[0107] A silicon interlayer insulating film is wet-etched afterroughening of the surface of a storage node. This makes it possible toincrease the capacitance and remove polysilicon residues from aroughened surface more reliably.

[0108] Obviously many modifications and variations of the presentinvention are possible in the light of the above teachings. It istherefore to be understood that within the scope of the appended claimsthe invention may by practiced otherwise than as specifically described.

[0109] The entire disclosure of a Japanese Patent Application No.11-148864, filed on May 27, 1999 including specification, claims,drawings and summary, on which the Convention priority of the presentapplication is based, are incorporated herein by reference in itsentirety.

1. A method of manufacturing a semiconductor device, comprising thesteps of: forming a pad insulating film, a polysilicon film, and asilicon nitride film sequentially on a semiconductor substrate; forminga trench portion for isolating device forming regions on saidsemiconductor substrate by selectively etching said silicon nitridefilm, polysilicon film, pad insulating film, and semiconductorsubstrate; embedding a silicon oxide film in said trench portion forisolating said device forming regions; removing said silicon nitridefilm, polysilicon film, and pad insulating film to expose a surface ofsaid semiconductor substrate; and forming a circuit element on theexposed surface of said semiconductor substrate; wherein saidpolysilicon film is removed by isotropic wet etching.
 2. The method ofmanufacturing a semiconductor device according to claim 1, wherein aheat treatment to said silicon oxide film embedded in said trenchportion is performed at a temperature of 1,050° C.
 3. The method ofmanufacturing a semiconductor device according to claim 1, wherein saidwet etching is performed by aqueous ammonia or a mixed solution ofaqueous ammonia and a hydrogen peroxide solution.
 4. The method ofmanufacturing a semiconductor device according to claim 1, wherein a CVDoxide film is formed on said silicon oxide film embedded in said trenchportion, following the step of removing said silicon nitride film andpolysilicon film.
 5. The method of manufacturing a semiconductor deviceaccording to claim 1, wherein said silicon oxide film embedded in saidtrench portion is oxidized, following the step of removing said siliconnitride film and polysilicon film.
 6. The method of manufacturing asemiconductor device according to claim 1, wherein a short-time, rapidheat treatment is performed on said silicon oxide film embedded in saidtrench portion, following the step of removing said silicon nitride filmand polysilicon film.
 7. The method of manufacturing a semiconductordevice according to claim 1, wherein said pad insulating film is removedby use of a hydrofluoric acid solution followed by a treatment with aphosphoric acid type solution, to expose a surface of said semiconductorsubstrate.
 8. The method of manufacturing a semiconductor deviceaccording to claim 1, wherein the step of removing said pat insulatingfilm includes the sub steps of: removing only thin portions of said padinsulating film to partially expose a surface of said semiconductorsubstrate; performing a wet treatment to remove a nitride layer fromsaid surface of said semiconductor substrate; and then removingremaining portions of said pad insulating film to expose a surface ofsaid semiconductor substrate.
 9. The method of manufacturing asemiconductor device according to claim 1, wherein ion implantation intosaid semiconductor substrate is performed after removing said siliconnitride film and polysilicon film, and prior to removing said padinsulating film.
 10. The method of manufacturing a semiconductor deviceaccording to claim 1, wherein said step of forming a circuit element onthe exposed surface of said semiconductor substrate includes thesub-steps of: forming at least a gate insulating film, a polysiliconfilm, and an upper insulating film sequentially on said exposed surfaceof said semiconductor substrate; forming agate electrode by patterningsaid upper insulating film, polysilicon film, and gate insulating filmby anisotropic etching; and performing isotropic wet etching to removepolysilicon on said surface of said semiconductor substrate.
 11. Amethod of manufacturing a semiconductor device, comprising the steps of:forming a pad insulating film, and a silicon nitride film sequentiallyon a semiconductor substrate; forming a trench portion for isolatingdevice forming regions on said semiconductor substrate by selectivelyetching said silicon nitride film, pad insulating film, andsemiconductor substrate; embedding a silicon oxide film in said trenchportion for isolating said device forming regions; removing said siliconnitride film, and pad insulating film to expose a surface of saidsemiconductor substrate; and forming a circuit element on the exposedsurface of said semiconductor substrate.
 12. The method of manufacturinga semiconductor device according to claim 11, wherein a CVD oxide filmis formed on said silicon oxide film embedded in said trench portion,following the step of removing said silicon nitride film.
 13. The methodof manufacturing a semiconductor device according to claim 11, whereinsaid silicon oxide film embedded in said trench portion is oxidized,following the step of removing said silicon nitride film.
 14. The methodof manufacturing a semiconductor device according to claim 11, wherein ashort-time, rapid heat treatment is performed on said silicon oxide filmembedded in said trench portion, following the step of removing saidsilicon nitride film.
 15. The method of manufacturing a semiconductordevice according to claim 11, wherein said pad insulating film isremoved by use of a hydrofluoric acid solution followed by a treatmentwith a phosphoric acid type solution, to expose a surface of saidsemiconductor substrate.
 16. The method of manufacturing a semiconductordevice according to claim 11, wherein the step of removing said patinsulating film includes the sub steps of: removing only thin portionsof said pad insulating film to partially expose a surface of saidsemiconductor substrate; performing a wet treatment to remove a nitridelayer from said surface of said semiconductor substrate; and thenremoving remaining portions of said pad insulating film to expose asurface of said semiconductor substrate.
 17. The method of manufacturinga semiconductor device according to claim 11, wherein ion implantationinto said semiconductor substrate is performed after removing saidsilicon nitride film, and prior to removing said pad insulating film.18. The method of manufacturing a semiconductor device according toclaim 11, wherein said step of forming a circuit element on the exposedsurface of said semiconductor substrate includes the sub-steps of:forming at least a gate insulating film, a polysilicon film, and anupper insulating film sequentially on said exposed surface of saidsemiconductor substrate; forming a gate electrode by patterning saidupper insulating film, polysilicon film, and gate insulating film byanisotropic etching; and performing isotropic wet etching to removepolysilicon on said surface of said semiconductor substrate.
 19. Themethod of manufacturing a semiconductor device according to claim 18,wherein said gate electrode is formed by patterning said upperinsulating film and a top layer portion of said polysilicon film byanisotropic etching and then patterning a remaining portion of saidpolysilicon film and said pad insulating film by isotropic wet etching.20. A method of manufacturing a semiconductor device, comprising thesteps of: forming a storage node on an interlayer insulating film thatis formed on a semiconductor substrate; roughening a surface of saidstorage node; and wet-etching a surface of said interlayer insulatingfilm.